ISSCC 2007 / SESSION 29 / ANALOG AND POWER MANAGEMENT TECHNIQUES / 29.2 29.2 A 5mA 0.6μm CMOS Miller-Compensated LDO Regulator with -27dB Worst-Case Power-Supply Rejection Using 60pF of On-Chip Capacitance

As dense digital circuitry is packed close to sensitive analog blocks for higher integration, SoC solutions are swamped in switching noise generated by digital circuits, RF blocks, and DCDC converters. In this harsh environment, linear regulators have to protect noise-sensitive analog blocks like VCOs and ADCs from coupled supply noise that has amplitudes on the order of hundreds of millivolts and frequency components in the range of tens of kilohertz to hundreds of megahertz [1-2]. Along with high power-supply rejection (PSR) performance over a wide frequency range, these regulators need to exhibit low dropout to allow them to operate at the low supply voltages characteristic of state-ofthe-art CMOS processes. Moreover, these LDOs need to be stable and reject noise without the aid of bulky external capacitors, using only on-chip capacitors that are constantly constrained in size by valuable silicon real estate [3-5]. Finally, these SoC LDOs are increasingly deployed at the point-of-load and hence need to supply currents in the range of 2 to 20mA [3-5].